verilog HDLBits刷题[Verification:Writing Testbenches]“Tb/clock”---Clock

1、题目You are provided a module with the following declaration:module dut ( input clk ) ;Write a testbench that creates one instance of module dut (with any instance name), and create a clock signal to drive the modules clk input. The clock has a period of 10 ps. The clock should be initialized to zero with its first transition being 0 to 1.2、分析有个模块的输入端口为clk需要写一个testbench产生clk信号驱动,并将所提供的模块进行例化3、代码module top_module ( ); reg clk; initial begin clk 1b0; end always #5 clk~clk; dut dut_inst(clk); endmodule4、结果