AXI_SLAVER代码问题求助！！！

求问各位大佬为什么这里在1处对arlen等信号赋值是赋不上值的但axi_arready却可以赋值上这是为什么怎么解决这个问题呢如果使用2则会延后一拍但这不是想要的效果。//-------------------------------------------------------------------------------- // axi_slv //-------------------------------------------------------------------------------- include axi_define.v module axi_slv ( // system signals input wire axi_aclk , input wire axi_arst_n , // AXI rd addr channel output reg axi_arready, input wire axi_arvalid, input wire [AXI_ID_WIDTH -1:0] axi_arid , input wire [AXI_ADDR_WIDTH -1:0] axi_araddr , input wire [AXI_LEN_WIDTH -1:0] axi_arlen , input wire [AXI_SIZE_WIDTH -1:0] axi_arsize , input wire [AXI_BURST_WIDTH -1:0] axi_arburst, input wire axi_arlock , input wire [AXI_CACHE_WIDTH -1:0] axi_arcache, input wire [AXI_PROT_WIDTH -1:0] axi_arprot , input wire [AXI_QOS_WIDTH -1:0] axi_arqos , // AXI rd data channel input wire axi_rready , output reg axi_rvalid , output reg [AXI_ID_WIDTH -1:0] axi_rid , output reg [AXI_DATA_WIDTH -1:0] axi_rdata , output wire [AXI_RESP_WIDTH -1:0] axi_rresp , output wire axi_rlast , // User input wire enable ); //-------------------------------------------------------------------------------- // register and I/O //-------------------------------------------------------------------------------- reg [AXI_ID_WIDTH -1:0] arid ; reg [AXI_ADDR_WIDTH -1:0] araddr ; reg [AXI_SIZE_WIDTH -1:0] arsize ; reg [AXI_LEN_WIDTH -1:0] arlen ; reg [AXI_BURST_WIDTH-1:0] arburst ; reg [AXI_LEN_WIDTH -1:0] beat_cnt; reg [15:0] get_delay_cnt; reg [AXI_DATA_WIDTH -1:0] data_mem [1023:0]; // Internal memory for data reg [5:0] curr_state, next_state; // Burst and resp type localparam AXI_BURST_FIXED 2b00; localparam AXI_BURST_INCR 2b01; localparam AXI_BURST_WRAP 2b10; localparam AXI_RESP_OKAY 2b00; localparam AXI_RESP_SLVERR 2b10; localparam AXI_RESP_DECERR 2b11; // Unified read/write FSM localparam ST_IDLE 6b00_0000; localparam ST_AR_HANDSHAKE 6b00_0001; localparam ST_R_HANDSHAKE 6b00_0010; // Loading data initial begin $readmemh(sine_wave.mem, data_mem); end assign axi_rlast (axi_rvalid axi_rready (beat_cnt arlen)) ? 1b1 : 1b0; assign axi_rresp AXI_RESP_OKAY; //-------------------------------------------------------------------------------- // FSM //-------------------------------------------------------------------------------- always (posedge axi_aclk or negedge axi_arst_n) begin if (!axi_arst_n) begin curr_state ST_IDLE; end else begin curr_state next_state; end end always (*) begin next_state curr_state; case (curr_state) ST_IDLE:begin if (enable) begin next_state ST_AR_HANDSHAKE; end else begin next_state ST_IDLE; end end ST_AR_HANDSHAKE:begin if (axi_arvalid axi_arready) begin next_state ST_R_HANDSHAKE; end else begin next_state ST_AR_HANDSHAKE; end end ST_R_HANDSHAKE:begin if (axi_rvalid axi_rready axi_rlast) begin next_state ST_IDLE; end else begin next_state ST_R_HANDSHAKE; end end default:begin next_state ST_IDLE; end endcase end always (posedge axi_aclk or negedge axi_arst_n) begin if (!axi_arst_n) begin axi_arready 1b0; axi_rvalid 1b0; axi_rid AXI_ID_WIDTHh0; axi_rdata AXI_DATA_WIDTHh0; araddr AXI_ADDR_WIDTHh0; arsize AXI_SIZE_WIDTHh0; arlen AXI_LEN_WIDTHh0 ; arburst AXI_BURST_WIDTHh0; beat_cnt AXI_LEN_WIDTHd0 ; get_delay_cnt 16d0; end else begin case (curr_state) ST_IDLE:begin axi_arready 1b0; axi_rvalid 1b0; axi_rid AXI_ID_WIDTHh0; axi_rdata AXI_DATA_WIDTHh0; araddr AXI_ADDR_WIDTHh0; arsize AXI_SIZE_WIDTHh0; arlen AXI_LEN_WIDTHh0 ; arburst AXI_BURST_WIDTHh0; beat_cnt AXI_LEN_WIDTHd0 ; get_delay_cnt 16d0; end ST_AR_HANDSHAKE:begin if (axi_arvalid !axi_arready) begin axi_arready 1b1; end else if (axi_arvalid axi_arready) begin axi_arready 1b0; // axi_rid axi_arid ; // araddr axi_araddr ; // arsize axi_arsize ; // arlen axi_arlen ; // arburst axi_arburst; end end ST_R_HANDSHAKE:begin araddr axi_araddr ; arsize axi_arsize ; arlen axi_arlen ; arburst axi_arburst; if (!axi_rvalid !axi_rready) begin if (get_delay_cnt DATA_GET_DELAY) begin axi_rvalid 1b1; get_delay_cnt 16d0; end else begin axi_rvalid 1b0; get_delay_cnt get_delay_cnt 1b1; end end else if (axi_rvalid axi_rready) begin axi_rvalid 1b0; axi_rid axi_arid ; axi_rdata data_mem[curr_addr]; beat_cnt beat_cnt 1; curr_addr curr_addr 1; end end default: ; endcase end end endmodule